The recovery in demand for PCs and smartphones will take time, leading to a halt in the upward trend of DRAM prices, remaining stable for two consecutive months. However, the rapid growth in demand for High Bandwidth Memory (HBM), essential for data center servers and generative AI, is expected to boost future DRAM prices as the production trend of HBM rises.

The Nikkei News reported on May 18th that the recovery in demand for PCs and smartphones will take time, leading to a halt in the upward trend of DRAM prices used in smartphones, PCs, and data center servers for temporary data storage.

In April 2024, the wholesale price (bulk transaction price) of the benchmark product DDR4 8Gb was around USD 1.95 per unit, and the price of the smaller capacity 4Gb product was around USD 1.50 per unit, both remaining unchanged from the previous month (March 2024) and marking the second consecutive month of stability.

As of February 2024, DRAM prices had risen for four consecutive months. DRAM wholesale prices are negotiated between memory manufacturers and customers monthly or quarterly. Reportedly, approximately 50% of DRAM demand comes from PCs and servers, while around 35% comes from smartphones.

The report indicated that the demand for HBM, essential for generative AI, is rapidly increasing, and market expectations for the production trend of HBM are expected to boost future DRAM price increases.

A source cited in the report, which is an Electronic product trader, noted that some major manufacturers have accepted the memory manufacturers’ price hike requests. A PC manufacturer source cited by the report also stated that DRAM wholesale prices from April to June are expected to rise by 5-10% compared to January to March.

Another source cited by the report stated that the facilities required to produce HBM are approximately three times larger than those needed for producing general DRAM. If HBM production increases, the production volume of other DRAMs will decrease, thereby driving up prices. Another source cited in the report stated that supply cannot keep up with demand, and pricing power is currently in the hands of memory manufacturers.

Read more

• [News] Samsung and SK Hynix Urgently Reallocate 20% of DRAM Production Capacity to Support Rising HBM demand
• [News] Three-way Contest for HBM Dominance, Uncertainties Surrounding China’s Supply Chain Involvement

(Photo credit: SK Hynix)

As the era of AI advances, following NVIDIA’s application to the Ministry of Economic Affairs (MOEA) for the “A+ Industrial Innovative R&D Program,”  which led to the establishment of the first R&D center in Asia and the creation of Taiwan’s largest AI supercomputer, “Taipei-1”, American AI chip giant AMD is set to follow suit.

According to a report from UDN, AMD plans to invest NTD 5 billion (roughly USD 155 million) to establish an R&D center in Taiwan and intends to apply for the A+ Industrial Innovative R&D Program from the MOEA, highlighting Taiwan’s critical role in AI chip design and manufacturing.

The MOEA has confirmed that AMD applied for the A+ Industrial Innovative R&D Program subsidy at the end of 2023. However, the funding for the program has already been exhausted. Therefore, funds must be allocated in the fifth phase of the A+ Industrial Innovative R&D Program, with the science and technology budget to be set for 2025.

This budget allocation must be approved by the new government administration. Additionally, MOEA officials stated that AMD must submit a concrete plan and gain approval from a review committee established by the Industrial Technology Department of the MOEA.

Previously, the MOEA’s substantial subsidies to global companies under the A+ Industrial Innovative R&D Program sparked mixed reactions within the industry. Some prominent local IC design companies criticized the MOEA, arguing that supporting global companies leads to competition against local businesses and drains valuable local R&D talent.

To avoid controversy, the MOEA has set forth four specific requirements for AMD.

First, they hope AMD will collaborate with Taiwanese IC design companies. Second, any AI servers developed should be manufactured in Taiwan. Third, at least 20% of the R&D workforce should be sourced from abroad, and high-level executives should be stationed in Taiwan. Fourth, AMD should partner with Taiwanese universities to cultivate talent jointly. The MOEA reports that AMD’s response has been very positive, and a thorough review of the application will take place in the second half of the year.

To date, the MOEA’s A+ Industrial Innovative R&D Program has approved subsidies only for two global companies, Micron and NVIDIA, providing them with NTD 4.722 billion (USD 146.48 million) and NTD 6.7 billion (USD 207.8 million), respectively. The MOEA believes this strategy helps solidify Taiwan’s competitive edge in the global semiconductor and AI sectors.

Read more

• [News] Qualcomm Commits to USD 700 Million Investment in Taiwan Over 5 Years in Settlement with Fair Trade Commission
• [News] AI Chip Alone Can’t Hold Up? AMD’s Fiscal Forecast This Quarter Reportedly Falls Short of Expectations

(Photo credit: AMD)

The world’s four major CSPs (Cloud Service Providers) – Microsoft, Google, Amazon, and META – are continuously expanding their AI infrastructure, with their combined capital expenditures projected to reach USD 170 billion this year. According to the industry sources cited in a report from Commercial Times, it’s pointed out that due to the surge in demand for AI chips and the increased area of silicon interposers, the number of chips that can be produced from a single 12-inch wafer is decreasing. This situation is expected to cause the CoWoS (Chip on Wafer on Substrate) production capacity under TSMC to remain in short supply.

Regarding CoWoS, according to TrendForce, the introduction of NVIDIA’s B series, including GB200, B100, B200, is expected to consume more CoWoS production capacity. TSMC has also increased its demand for CoWoS production capacity for the entire year of 2024, with estimated monthly capacity approaching 40,000 by the year-end, compared to an increase of over 150% from the total capacity in 2023. A possibility exists for the total production capacity to nearly double in 2025.

However, with NVIDIA releasing the B100 and B200, the interposer area used by a single chip will be larger than before, meaning the number of interposers obtained from a 12-inch wafer will further decrease, resulting in CoWoS production capacity being unable to meet GPU demand. Meanwhile, the number of HBM units installed is also multiplying.

Moreover, in CoWoS, multiple HBMs are placed around the GPU, and HBMs are also considered one of the bottlenecks. Industry sources indicate that HBM is a significant challenge, with the number of EUV (Extreme Ultraviolet Lithography) layers gradually increasing. For example, SK Hynix, which holds the leading market share in HBM, applied a single EUV layer during its 1α production phase. Starting this year, the company is transitioning to 1β, potentially increasing the application of EUV by three to four times.

In addition to the increased technical difficulty, the number of DRAM units within HBM  has also increased with each iteration. The number of DRAMs stacked in HBM2 ranges from 4 to 8, while HBM3/3e increases this to 8 to 12, and HBM4 will further raise the number of stacked DRAMs to 16.

Given these dual bottlenecks, overcoming these challenges in the short term remains difficult. Competitors are also proposing solutions; for instance, Intel is using rectangular glass substrates to replace 12-inch wafer interposers. However, this approach requires significant preparation, time, and research and development investment, and breakthroughs from industry players are still awaited.

Read more

• [News] TSMC’s Advanced Packaging Capacity Fully Booked by NVIDIA and AMD Through Next Year
• [Insights] Big Four CSPs Continue to Shine in Q1 2024 Financial Reports, AI Returns Garnering Attention

(Photo credit: NVIDIA)

As Apple keeps advancing in AI as well as developing its own in-house processors, industry sources indicated that the tech giant’s Chief Operating Officer (COO) Jeff Williams recently made a visit to TSMC, and was personally received by TSMC’s President, C.C. Wei, according a report by Economic Daily News.

The low-profile visit was made to secure TSMC’s advanced manufacturing capacity, potentially 2nm process, booked for Apple’s in-house AI-chips, according to the report.

Apple has been collaborating with TSMC for many years on the A-series processors used in iPhones. In recent years, Apple initiated the long-term Apple Silicon project, creating the M-series processors for MacBook and iPad, with Williams playing a key role. Thus, his recent visit to Taiwan has garnered significant industry attention.

Apple did not respond to the rumor. TSMC, on the other hand, has maintained its usual stance, not commenting on market speculations related to specific customers.

According to an earlier report from The Wallstreet Journal, Apple has been working closely with TSMC to design and produce its own AI chips tailored for data centers in the primary stage. It is suggested that Apple’s server chips may focus on executing AI models, particularly in AI inference, rather than AI training, where NVIDIA’s chips currently dominate.

Also, in a bid to seize the AI PC market opportunity, Apple’s new iPad Pro launched in early May has featured its in-house M4 chip. In an earlier report by Wccftech, Apple’s M4 chip adopts TSMC’s N3E process, aligning with Apple’s plans for a major performance upgrade for Mac.

In addition to Apple, with the flourishing of AI applications, TSMC has also reportedly beening working closely with the other two major AI giants, NVIDIA and AMD. It’s reported by the Economic Daily News that they have secured TSMC’s advanced packaging capacity for CoWoS and SoIC packaging through this year and the next, bolstering TSMC’s AI-related business orders.

Read more

• [News] Apple M4 Incoming, Boosting TSMC’s 3nm Production
• [News] Apple Unveiled M4 Chip for AI, Heralding a New Era of AI PC

(Photo credit: TSMC)

In addition to the aggressive overseas expansion plans recently, TSMC also demonstrates its ambition of increasing specialty capacity, targeting to be expanded by 50% by 2027, according to a report by AnandTech. A key driver of this demand will be TSMC’s forthcoming specialty node, N4e, a 4nm-class ultra-low-power production node.

Citing Kevin Zhang, TSMC’s Senior Vice President of the Business Development and Overseas Operations Office, the report revealed that TSMC plans to expand its specialty capacity by up to 1.5 times in the next four to five years. To accomplish this goal, it would not only convert existing capacity, but construct new fab space dedicated to specialty processes.

TSMC offers a range of specialty nodes catering to various applications such as power semiconductors, mixed analog I/O, and ultra-low-power applications (e.g., IoT), according to the report. Currently, the semiconductor giant’s most advanced specialty node is N6e, a variant derived from N7/N6 that accommodates operating voltages ranging from 0.4V to 0.9V. With N4e, TSMC aims to support voltages below 0.4V.

According to the materials TSMC provided in its latest earnings call, in the first quarter, HPC accounted for 46% of its total revenue, while IoT-related and automotive applications accounted for 6% of its total revenue, respectively. All the applications mentioned above are closely connected to specialty nodes.

TSMC’s overseas expansion plans are also closely related to its focus on specialty nodes. At the grand opening of JASM’s first Kumamoto plant in February, TSMC Chairman Mark Liu stated that JASM would use the latest green manufacturing practices to produce best-in-class specialty semiconductor technology.

Read more

• [News] TSMC Reportedly Prepares Next-generation HBM4 Manufacturing, Utilizing 12nm and 5nm Process Nodes

(Photo credit: TSMC)