[Insights] Memory Spot Price Update: DRAM Price Down Again Due to Chip Supply Increase Led By Samsung

According to TrendForce’s latest memory spot price trend report, sellers, in particular Samsung, have increased the chip supply, therefore pushing DRAM prices downward, while DDR4 products suffer from higher inventory. Regarding NAND Flash prices, the retail market is less willing in replenish orders, together with how wafer prices have been surging from the bottom, the depletion of spot prices could carry on. Details are as follows:

DRAM Spot Price:

The spot market has yet to show a demand turnaround; and sellers, in particular Samsung, have increased the chip supply, thereby pushing prices back down again. Looking at different types of DRAM products, module houses and channels have relatively high inventory levels for DDR4 products. Hence, the downward pressure on spot prices of DDR4 products is greater compared with spot prices of DDR5 products. Overall, even though contract prices have again registered significant increases in 2Q24, this rally has no positive effect on spot prices. Instead, spot transactions continue to show declining quantity, and the downward price pressure has become more pronounced. The average spot price of mainstream chips (i.e., DDR4 1Gx8 2666MT/s) has dropped by 1.19% from US$1.940 last week to US$1.917 this week.

NAND Flash Spot Price:

The Chinese government’s cracking down on smuggling of memory products, as well as the persistently sluggish demand from the retail market, have prompted module houses to amplify their sales intensity to actively pursue transactions, which led to a loosening in prices. Without replenishment of orders within the retail market, together with how wafer prices have surged from rock bottom to nearly 80% by now, the depletion of spot prices could carry on in the near future. Spot price for 512Gb TLC wafers has dropped by 2.61% this week, arriving at US$3.579.


[News] Micron Slightly Raises Capital Expenditure for 2024, HBM Expected to Further Drive Revenue Growth in 2025

Micron Technology Inc., the American memory giant, has slightly increased its capital expenditure for this year (2024) and has not updated its financial forecasts for the second quarter (March to May).

According to reports from, and other global news outlets, Matt Murphy, the CFO of Micron, stated on May 21st that the company’s capital expenditure forecast for 2024 is expected to reach approximately USD 8 billion, up from the previous estimate of USD 7.5 billion. This increase is primarily attributed to investments in High Bandwidth Memory (HBM).

Micron’s Chief Operating Officer, Manish Bhatia, stated that the scale of the HBM business is expected to expand to several billion dollars in the 2025 fiscal year.

As per a previous report by Economic Daily News, Micron’s current 8-layer stacking model offers the advantage of higher heat dissipation efficiency, as fewer layers allow for better cooling, ensuring stable chip performance. Additionally, Micron is planning to launch a 12-layer stacked 36Gb DRAM chip. Per a report from Tom’s Hardware, this new chip’s capacity is expected to be 50% greater than that of the previous 8-layer stack.

In March, Micron CEO Sanjay Mehrotra indicated that the company’s HBM earmarked for AI applications are sold out for 2024, with much of the 2025 supply already allocated.

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(Photo credit: Micron)

Please note that this article cites information from Reuters and


[News] Fabs Reportedly Depleting Inventory, Silicon Wafer Orders Expected to Resume in H2

Fab inventories have declined for two consecutive quarters, indicating that reducing excess stock may currently be the semiconductor industry’s top priority. According to industry sources cited in a report from Commercial Times, fabs are predicted to wait until the second half of 2024 to resume ordering silicon wafers.

According to the latest quarterly analysis report from SEMI, a major microelectronics association, global silicon wafer shipments in the first quarter of 2024 reached 2,834 million square inches (MSI), marking a 5.4% decrease from the previous quarter and a 13.2% decrease from the same period last year.

SEMI attributes this decline in silicon wafer shipments to the continuing decline in IC fab utilization and inventory adjustments. Consequently, shipments of silicon wafers of all sizes experienced negative growth in the first quarter of 2024.

Industry sources cited by the same report note that, based on recent trends in foundry orders, apart from TSMC, other semiconductor manufacturers have seen capacity utilization rates around 70%. Among these, DRAM and Flash memory wafer shipments have shown year-on-year increases of 20.3% and 1%, respectively, indicating better performance compared to previous periods.

Japanese silicon wafer manufacturer Sumco recently announced in its financial report that in the first quarter, overall demand for 12-inch silicon wafers had bottomed out. Demand for logic chips used in AI and DRAM had increased. However, for applications outside of AI, customers continued to adjust their production.

Sumco estimates that due to customer production adjustments and the recovery of silicon wafer demand, it may take until the second half of 2024 for the situation to improve.

Industry sources cited by Economic Daily News believe that most IC design companies have returned to normal days of inventory (DOI) and are prioritizing urgent orders for foundries. However, the inventory levels of fabs and memory fabs remain historically high, so they will primarily focus on digesting existing long-term contracts (LTA) in the short term.

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(Photo credit: TSMC)

Please note that this article cites information from Commercial Times and SEMI.


[News] TSMC More Ambitious on CoWoS Capacity Expansion, Targeting 60% CAGR by 2026

As the demands for AI and HPC processors keep their momentum, driving the usage of advanced packaging technologies, TSMC revealed plans to further expand its chip-on-wafer-on-substrate (CoWoS) capacity at a compound annual rate (CAGR) of over 60% until at least 2026, according to a report by AnandTech.

According to its latest roadmap revealed at the company’s European Technology Symposium earlier, TSMC would now be able to more than quadruple its CoWoS capacity from 2023 levels by the end of 2026, the report indicated.

Last year, the foundry leader announced plans to more than double its CoWoS capacity by the end of 2024, but now it needs to be more ambitious, not only to meet existing demand but also address the future market.

TSMC is also preparing additional versions of CoWoS (specifically CoWoS-L) to support building system-in-packages (SiPs) with up to eight reticle sizes, just in case that increasing CoWoS capacity four-fold over three years may still be insufficient, the report said.

In addition to CoWoS, TSMC also plans to expand its system-on-integrated chips (SoIC) capacity at a CAGR of 100% through 2026, indicating that its SoIC capacity will increase eight-fold from 2023 levels by the end of 2026, according to AnandTech.

When it comes to the latest overseas expansion plans regarding major Taiwanese foundries, TSMC’s Kumamoto Fab 1, a joint investment between TSMC, Sony Semiconductor Solutions Corporation, and Denso Corporation, was inaugurated in February. Construction of the second Kumamoto fab is slated to begin by the end of 2024, with operations starting by the end of 2027.

UMC, Taiwan’s second-largest wafer foundry, announced on May 21st the arrival of the first equipment tools for phase 3 expansion at its Fab12i located in Singapore. According to a report by CNA, UMC anticipates the construction of the facility will be completed by mid-year. However, due to adjustments in customer orders, mass production has been delayed by six months to early 2026.

In October, 2023, Powerchip Semiconductor Manufacturing Corporation (PSMC), in collaboration with SBI Holdings, Inc., announced plans regarding its first semiconductor wafer plant in Japan, which is expected to be located in the Second Northern Sendai Central Industrial Park in Ohira Village, Kurokawa District, Miyagi Prefecture (Second Northern Sendai Central Industrial Park).

Previous reports indicated that PSMC plans to construct multiple plants, with the first phase potentially starting construction as early as 2024, involving an investment of around JPY 400 billion (USD 2.6 billion).

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(Photo credit: TSMC)


Please note that this article cites information from AnandTech and CNA.

[News] Intel’s Lunar Lake Bundled Memory Reportedly Causes Uproar in the PC Supply Chain

On May 20th, Intel announced that the release date for its next-generation processor, Lunar Lake, has been moved up, with official shipments expected in the third quarter. The NPU performance is set to reach 45 TOPS. However, per a report from Economic Daily News, the industry is puzzled by the fact that this chip is bundled with 16GB and 32GB memory, with Intel holding the specification control tightly. Reportedly, this move has disrupted the industry order, and PC manufacturers are said to be privately expressing their dissatisfaction.

It is expected that 20 brands will release 80 models featuring this processor. Combined shipments of Metro Lake and Lunar Lake this year are projected to reach 40 million units. Unlike the previous generation, Lunar Lake’s packaging design integrates LPDDR5x memory into a single package, emphasizing low power consumption.

On May 20th, Microsoft launched its next-generation AI PCs, equipped with a more powerful AI assistant, Copilot, and new features. It also established a new standard for AI PC architecture, “Copilot+ PC.” The initial products all feature Qualcomm’s “Snapdragon X Elite” processors designed with Arm architecture.

Qualcomm’s CPUs in the new PCs are equipped with a Neural Processing Engine (NPE) designed specifically for AI applications, boasting 45 TOPS. This, as per another report from the Economic Daily News, results in a 58% increase in speed and extended battery life compared to Apple’s latest top-tier MacBook, which uses the M3 chip. Additionally, they support Microsoft’s AI chatbot, Copilot.

Intel, on the other hand, made a rare announcement, revealing that its next-generation Lunar Lake will have a total performance exceeding 100 TOPS, with the NPU alone exceeding 45 TOPS—nearly three times that of the previous generation. Additionally, the CPU and GPU combined computing power will exceed 60 TOPS, making it the second qualified processor for Microsoft’s Copilot+ PC platform.

However, it is important to note that according to Intel’s plans, the new generation processors Ultra 5/7/9 will be bundled with memory and shipped together with the CPU. Specifically, the high-end Ultra 9 will be bundled with 32GB of memory, while the Ultra 5 and Ultra 7 will have 16GB and 32GB versions. Per Microsoft’s recommendations, AI PCs need at least 16GB of memory. While Intel’s approach meets this requirement, it limits the ability of brands to adjust specifications and leaves memory manufacturers out of the loop.

In simpler terms, there is still a demand for 8GB memory in lower-end notebooks, and high-end laptops can require more than 64GB of memory. However, Intel’s Lunar Lake constraints make it difficult to plan both high-end and entry-level versions. Industry sources cited in the same report from Economic Daily News indicate that Intel’s next-generation Arrow Lake will not be bundled with memory.

Reportedly, industry sources also state that procurement contracts with memory suppliers have traditionally been long-term, accounting for annual memory requirements. Now, Intel’s bundling of memory with its single platform changes the industry’s ecosystem. Previously, PC brands would develop various combinations (CPU + memory + SSD capacity) for their product lines. However, with Intel defining five laptop CPU + memory specifications, it limits the customization capabilities of PC brands.

With Intel launching Lunar Lake early, AMD is set to counter with its next-generation AI processor Ryzen series named Strix Point in the fourth quarter. The Strix Point processor will feature AI processing power exceeding 50 TOPS, and there will also be an APU, Strix Halo, expected to launch around the end of the year with performance exceeding 60 TOPS, making it a significant player in AI computing power.

CEO Pat Gelsinger recently demonstrated the performance of the Lunar Lake processor, emphasizing that its total AI workload exceeds 100 TOPS, with the NPU contributing 45 TOPS. The CPU features Lion Cove architecture P-cores and Skymont architecture E-cores, while the GPU and CPU together provide over 60 TOPS of computing power. This means Intel’s chip AI performance will be more than three times that of current products, with a total combined performance exceeding 100 TOPS.

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(Photo credit: Intel)

Please note that this article cites information from Intel and Economic Daily News.

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