In a bid to enhance its foundry capabilities, Samsung is earnestly integrating hybrid bonding technology. According to industry sources, Applied Materials and Besi Semiconductor are establishing equipment for hybrid bonding at the Cheonan Campus, slated for use in next-generation packaging solutions like X-Cube and SAINT.

According to a report from South Korean media outlet The Elec, industry sources have indicated that Applied Materials and Besi Semiconductor are installing hybrid bonding equipment at Samsung’s Cheonan Campus, a key site for advanced packaging production. Officials from the South Korean industry also mentioned that a production line is currently under construction, with the equipment intended for non-memory packaging.

Compared to existing bonding methods, hybrid bonding enhances I/O and wiring lengths. Samsung’s latest investment is expected to strengthen its advanced packaging capabilities, introducing the X-Cube utilizing hybrid bonding technology.

Industry sources cited by the report have suggested that hybrid bonding could also be applied to Samsung’s SAINT (Samsung Advanced Interconnect Technology) platform, which the company began introducing this year. The platform includes three types of 3D stacking technologies: SAINT S, SAINT L, and SAINT D.

SAINT S involves vertically stacking SRAM on logic chips such as CPUs. SAINT L involves stacking logic chips on top of other logic chips or application processors (APs). SAINT D entails vertical stacking of DRAM with logic chips like CPUs and GPUs.

TSMC, the leading semiconductor foundry, also offers hybrid bonding in its System on Integrated Chip (SoIC) for 3D packaging services, which is similarly provided by Applied Materials and Besi Semiconductor. Intel has also applied hybrid bonding technology in its 3D packaging technology, Foveros Direct, which was commercialized last year.

Reportedly, industry sources anticipate that Samsung’s investment in hybrid bonding facilities is poised to attract major clients such as NVIDIA and AMD. This is because the demand for hybrid bonding among fabless customers is steadily increasing.

(Photo credit: Samsung)

In the surge of AI advancements, a CoWoS expansion wave is rapidly underway, with TSMC showcasing ongoing ambitions in advanced packaging.

According to Monet DJ, recent industry reports suggest that TSMC is revising upward its capacity plans for SoIC (System-on-Integrated-Chips). By the end of this year, monthly production capacity is expected to jump from around 2,000 units in late 2023 to 5,000-6,000 units, addressing robust demand in the future for AI and HPC.

TSMC’s SoIC represents an industry-first high-density 3D chip stacking technology. Through the Chip on Wafer (CoW) packaging technique, it enables heterogeneous integration of chips with different sizes, functions, and nodes. Production has commenced at its advanced backend Fab 6 in Zhunan.

Quoting industry sources, Money DJ reports that SoIC’s monthly capacity was initially set to expand to 3,000-4,000 units this year from 2,000 units at the end of last year. However, it is now revised upward to 5,000-6,000 units, with a goal to double the capacity by 2025.

CoWoS, a mature technology with 15 years of development, is estimated to reach a monthly capacity of 30,000-34,000 units by the end of this year. TSMC is banking on its globally dominant 3D stacking technology with SoIC. The debut of major customer AMD MI300 utilizing SoIC with CoWoS is seen as pivotal. If successful, AMD could dominate the AI server sector, making TSMC’s SoIC a significant achievement.

Furthermore, Apple, TSMC’s largest customer, is reportedly keenly interested in SoIC. It is said to adopt SoIC with Hybrid Molding technology, currently in small-scale trial production and expected to enter mass production in 2025-2026. The plan is to apply it in products like Mac and iPad, offering cost advantages over current solutions.

As for another major customer of TSMC’s advanced packaging, NVIDIA, although high-end products currently favor CoWoS packaging, the industry anticipates the future integration of SoIC technology.

(Image: TSMC)

Taiwanese Semiconductor testing and packaging giant ASE announced today that its subsidiary, ASE Semiconductor, will lease the plant in Nanzih, Kaohsiung, owned by Taiwan’s ASE Test Inc., to expand its packaging capacity.

In the announcement, ASE Holdings revealed that ASE Semiconductor would lease a plant in Nanzih District, Kaohsiung, from its subsidiary ASE Test Inc. The total floor area of the building is approximately 15,600 square meters, with an estimated total usage rights asset value of NTD 742 million (approximately USD 23.8 million).

ASE Holdings stated that the primary purpose of this move is to optimize the overall planning and efficient utilization of plant space within the group, as well as to expand ASE’s packaging capacity.

According to CNA’s report, industry sources believe that ASE’s primary objective with this expansion is to enhance its production capacity for advanced packaging of Artificial Intelligence (AI) chips, but it is not directly related to CoWoS packaging.

Market insiders point out that ASE Holdings has been collaborating with foundry on technologies related to advanced packaging interposers and has CoWoS solutions. The earliest expected time for mass production is by the end of this year or early next year.

Reportedly, according to data, ASE’s Kaohsiung plant contributes to approximately 20% of ASE Holding’s overall revenue. The plant primarily provides services such as packaging, wafer bumping and probing, materials, and final testing.

The Kaohsiung plant is also establishing several smart plants, focusing on high-end processes, including Fan-Out packaging, System-in-Package (SiP), wafer bumping, and FlipChip packaging. These technologies find applications in various fields, including automotive, medical, IoT, high-speed computing, artificial intelligence, and application processors.

ASE actively positions itself in various advanced packaging technologies. Notably, the Fan-Out Chip on Substrate with Bridge (FOCoS-Bridge) packaging technology integrates multiple Application-Specific Integrated Circuits (ASICs) and High Bandwidth Memory (HBM), targeting the customized AI chip advanced packaging market.

In addition, ASE Semiconductor has introduced a cross-platform integrated design tool that combines several advanced packaging technologies, addressing the demands of advanced packaging for AI chips.

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(Photo credit: ASE)

Following TSMC’s first plant built in Japan’s Kumamoto Prefecture, Samsung has also chosen Yokohama as the location for its new facility in Japan.

According to Japanese media NHK’s report, South Korean Samsung Electronics has decided the establishment of a new semiconductor research and development center in Yokohama, Japan. with a total investment of JPY 40 billion (approximately USD 278 million).

The Japanese government is set to provide half of the total subsidy for this investment. The project is expected to commence next year and will focus on the research and development of advanced packaging.

Additionally, Samsung plans to hire around 100 local engineers in Japan and is cautiously evaluating the possibility of collaboration with Japanese research organizations.

NHK, citing sources, reported that Japanese Prime Minister Kishida Fumio plans to announce this expanded investment in Japan soon.

Given the continuous competition between China and the United States in the semiconductor sector, the calls for strengthening the domestic semiconductor supply chain in Japan have grown louder.

Consequently, the Japanese government has been encouraging foreign chipmakers to establish a presence in Japan, aiming to reinforce domestic supply chains.

As of May this year, Kishida Fumio met with seven semiconductor giants, including Intel, Samsung, Micron, and TSMC. The meeting demonstrated a commitment to revitalize Japan’s semiconductor industry. At that time, rumors about Japan providing subsidies to Samsung already existed, sparking market discussions.

(Photo credit: Samsung)

On November 30th, Apple revealed an extension of its partnership with Amkor in the advanced packaging sector within the United States. Apple proudly proclaimed its role as the inaugural and principal client for Amkor’s recently established facility in Peoria, Arizona. In this collaboration, Amkor will handle the packaging of Apple chips manufactured at the nearby TSMC’s wafer fab. Worth noting, Apple is also TSMC’s leading customer at the Arizona fab.

Jeff Williams, Apple’s CEO, emphasized Apple’s unwavering commitment to American manufacturing, stating that they will continue expanding investments in the U.S. Apple silicon’s groundbreaking performance capabilities have enabled users to accomplish unprecedented tasks. The announcement highlights the anticipation of Apple silicon being manufactured and packaged in Arizona.

According to the press release, Apple and Amkor have been collaborating for over a decade, packaging chips extensively used in all Apple products. Concerning the new factory, Amkor will invest approximately $2 billion, and upon completion, it will employ over 2,000 people.

Apple also underscores that the investment in advanced manufacturing is part of the company’s commitment in 2021 to invest USD 430 billion in the U.S. economy over five years. Currently, Apple is working towards achieving this goal through direct spending with American suppliers, data center investments, U.S. capital expenditures, and other domestic expenditures.

On the other hand, Amkor outlined plans to establish a state-of-the-art manufacturing campus featuring an expansive 500,000 square feet of cleanroom space. The primary objective of the initial phase is to initiate production within the next two to three years.

Amkor aims to provide cutting-edge technology catering to high-volume semiconductor advanced packaging and testing, specifically supporting crucial markets such as high-performance computing, automotive, and communications. The newly proposed production facility will be strategically located within a semiconductor hub, surrounded by front-end wafer fabs, IDM, and existing or expanding suppliers in the field, including TSMC, Intel, Applied Materials, ASML, and others.

“Amkor has been a strategic OSAT partner to TSMC for many years,” said Dr. C.C. Wei, CEO of TSMC. “TSMC applauds Amkor for investing in the future of the semiconductor industry with us in Arizona. We share Amkor’s excitement for its significant investment and the value this facility will bring to TSMC, our customers, and the ecosystem.”

Giel Rutten, CEO from Amkor, indicated the incorporation of this new U.S. facility with Amkor’s advanced facilities across Asia and Europe serves to strengthen global extension and fosters both global and regional supply chains. Amkor’s investment is positioned to bolster them in advanced packaging and testing, concurrently reaffirming the commitment to expanding chip manufacturing in the United States.

According from the financial reports, Amkor’s two largest clients are Apple and Qualcomm. Apple accounted for 20.6% and Qualcomm 10.1%. of Amkor’s USD 7.1 billion in revenue last year.
(Image: Amkor)

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