Samsung’s flagship mobile processor, the Exynos 2400, produced using the 4LPP+ process technology, currently boasts a yield rate of approximately 60%, as per sources cited by TechNews. While this figure falls short of competitors, notably TSMC’s N4P process technology with yields surpassing 70%, it represents a significant improvement from Samsung’s own 25% yield rate over a year ago.

Samsung’s Exynos 2400 flagship mobile processor is the company’s first to utilize Fan-Out Wafer-Level Packaging (FOWLP). Samsung claims that FOWLP technology enhances heat resistance by 23% and boosts multicore performance by 8%. Consequently, the Exynos 2400 mobile processor delivers commendable performance in the latest 3DMark Wild Life benchmark tests.

In fact, Samsung previously announced plans to commence mass production of the SF3 chip in the second half of 2024, followed by the introduction of its 2-nanometer process technology between 2025 and 2026.

Industry sources cited in the report also indicate that Samsung’s foundry business has begun trial production for its second-generation 3-nanometer process technology, SF3. Furthermore, the company aims to increase its yield rate to over 60% within the next six months.

It is noteworthy that Samsung’s 3nm technology is highly aggressive compared to TSMC’s approach, which will transition to GAA transistors with its 2nm process. Samsung’s first-generation 3nm process already incorporates GAA transistor technology, specifically the MBCFET (Multi-Bridge Channel Field-Effect Transistor), known as SF3E, or 3GAE technology.

As per WeChat account ic211ic cited sources in the report, Samsung’s 3nm GAA technology utilizes wider nanosheets compared to the narrow nanowire GAA technology, offering higher performance and energy efficiency. With the 3nm GAA technology, Samsung can adjust the channel width of nanosheet transistors to optimize power consumption and performance, meeting diverse customer requirements.

Additionally, the flexibility of GAA design is highly advantageous for Design-Technology Co-Optimization (DTCO), contributing to achieving better Power, Performance, and Area (PPA) advantages.

In comparison to Samsung’s 5nm process, the first-generation 3nm process reduces power consumption by 45%, enhances performance by 23%, and decreases chip area by 16%. The upcoming second-generation 3nm process is expected to further reduce power consumption by 50%, boost performance by 30%, and reduce chip area by 35%.

(Photo credit: Samsung)

In a bid to enhance its foundry capabilities, Samsung is earnestly integrating hybrid bonding technology. According to industry sources, Applied Materials and Besi Semiconductor are establishing equipment for hybrid bonding at the Cheonan Campus, slated for use in next-generation packaging solutions like X-Cube and SAINT.

According to a report from South Korean media outlet The Elec, industry sources have indicated that Applied Materials and Besi Semiconductor are installing hybrid bonding equipment at Samsung’s Cheonan Campus, a key site for advanced packaging production. Officials from the South Korean industry also mentioned that a production line is currently under construction, with the equipment intended for non-memory packaging.

Compared to existing bonding methods, hybrid bonding enhances I/O and wiring lengths. Samsung’s latest investment is expected to strengthen its advanced packaging capabilities, introducing the X-Cube utilizing hybrid bonding technology.

Industry sources cited by the report have suggested that hybrid bonding could also be applied to Samsung’s SAINT (Samsung Advanced Interconnect Technology) platform, which the company began introducing this year. The platform includes three types of 3D stacking technologies: SAINT S, SAINT L, and SAINT D.

SAINT S involves vertically stacking SRAM on logic chips such as CPUs. SAINT L involves stacking logic chips on top of other logic chips or application processors (APs). SAINT D entails vertical stacking of DRAM with logic chips like CPUs and GPUs.

TSMC, the leading semiconductor foundry, also offers hybrid bonding in its System on Integrated Chip (SoIC) for 3D packaging services, which is similarly provided by Applied Materials and Besi Semiconductor. Intel has also applied hybrid bonding technology in its 3D packaging technology, Foveros Direct, which was commercialized last year.

Reportedly, industry sources anticipate that Samsung’s investment in hybrid bonding facilities is poised to attract major clients such as NVIDIA and AMD. This is because the demand for hybrid bonding among fabless customers is steadily increasing.

(Photo credit: Samsung)

Samsung’s latest financial report reveals that the fourth-quarter shipments of DRAM and NAND Flash in 2023 exceeded previous expectations, reflecting an improvement in market demand. Samsung will continue selectively adjusting the production capacity of specific DRAM and NAND Flash products to boost prices.

Samsung Electronics’ memory business is expected to return to profit in the first quarter of 2024, signaling a recovery in the memory industry. Commercial Times reports that due to inventory improvements, Samsung’s utilization rate of DRAM is projected to increase from 70% in the fourth quarter of 2024 to 81% in the first quarter of 2024, and further rise to 89% in the second quarter.

According to industry sources cited in the Commercial Times’ report, Samsung’s fourth-quarter shipments of DRAM and NAND Flash in 2023 exceeded previous expectations. This was primarily attributed to Samsung’s memory experiencing a smaller price increase compared to its competitors, thereby accelerating the pace of inventory clearance, particularly in the case of DRAM, where improvements were more significant.

Samsung is expected to continue selectively adjusting the production of DRAM and NAND Flash products. As the first quarter is typically a slow season for the industry, Samsung anticipates a sequential decline in DRAM and NAND Flash shipments in the first quarter of 2024. However, prices are expected to continue rising.

Due to the destocking of Samsung’s DRAM for eight to ten weeks, it is expected to return to normal level by the end of the 1st quarter of 2024. Meanwhile, NAND Flash inventory is projected to normal level within the first half of 2024.

At the same time, Samsung plans to commence production of HBM3e 24GB products in the first half of 2024, with HBM3e 36GB products slated for production in the second half of the year, with progress ahead of schedule. Additionally, the development of the next-generation HBM4 is currently underway, with samples expected to be released in 2025 and mass production in 2026.

As per sources cited by the Commercial Times, reportedly, regarding HBM3 and HBM3e, HBM3 used in AI servers is still exclusively supplied by SK Hynix, with the highest yield in backend packaging, followed by Micron. Meanwhile, the report also indicates that HBM3e is expected to begin mass production in the first quarter of 2024. Micron’s outsourcing of backend TSV and stacking to TSMC has accelerated the product’s production speed.

As for the higher-spec HBM4, TrendForce expects its potential launch in 2026. With the push for higher computational performance, HBM4 is set to expand from the current 12-layer (12hi) to 16-layer (16hi) stacks, spurring demand for new hybrid bonding techniques. HBM4 12hi products are set for a 2026 launch, with 16hi models following in 2027.

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• [News] Samsung and Micron Rumored to Increase DRAM Prices by 15% to 20% in the First Quarter

(Photo credit: Samsung)

From the current landscape of publicly available DRAM technologies, the industry is expected to perceive 3D DRAM as one of the solutions to the challenges faced by DRAM technology, marking it as a pivotal direction for the future memory market.

Is 3D DRAM similar to 3D NAND? How will the industry address technological bottlenecks such as size limitations? What are the strategies of major players in the field?

• Understanding 3D DRAM Technology

The circuitry of DRAM consists of a transistor and a capacitor, where the transistor is responsible for transmitting electrical currents to write or read information (bits), while the capacitor stores the bits.

DRAM finds wide application in modern digital electronic devices such as computers, graphics cards, portable devices, and gaming consoles, due to its low cost and high capacity memory.

The development of DRAM primarily focuses on increasing integration by reducing circuit line widths. However, as line widths reach the 10nm range, physical limitations such as capacitor current leakage and interference significantly increase.

To address these issues, the industry has introduced new materials and equipment like high dielectric constant (high-K) deposition materials and Extreme Ultraviolet (EUV) devices.

Nevertheless, from the perspective of chip manufacturers, miniaturizing the manufacturing of 10nm or more advanced chips remains a significant challenge in current technology research and development. Additionally, the competition for advanced processes, particularly at 2nm and below, has intensified recently.

In an era marked by continuous technological advancements, the semiconductor industry has turned its attention to the evolution of NAND technology. To overcome scaling limitations, transistors are transitioning from a planar to a 3D architecture, increasing the number of storage units per unit area. This concept of 3D DRAM architecture has entered the public sphere.

In traditional DRAM, transistors are integrated on a flat plane. However, in 3D DRAM, transistors are stacked into multiple layers, thereby dispersing the transistors. It is believed that adopting a 3D DRAM structure can widen the gaps between transistors, reducing leakage currents and interference.

From a theoretical perspective, 3D DRAM technology breaks the conventional paradigm of memory technology. It is a novel storage method that stacks storage cells above logic units, enabling higher capacities within a unit chip area.

In terms of differentiation, traditional DRAM requires complex operational processes for reading and writing data, whereas 3D DRAM can directly access and write data through vertically stacked storage units, significantly enhancing access speeds. The advantages of 3D DRAM not only include high capacity and fast data access but also low power consumption and high reliability, meeting various application needs.

In terms of application areas, the high speed and large capacity of 3D DRAM will help improve the efficiency and performance of high-performance computing. The compact size and large capacity of 3D DRAM make it an ideal memory solution for mobile devices. The large capacity and low power consumption characteristics of 3D DRAM can meet the real-time data processing and transmission requirements of the Internet of Things (IoT) field.

Furthermore, since the advent of the AI era with ChatGPT, AI applications have surged, and AI servers are expected to become a strong driving force for the long-term growth in storage demand.

Micron’s chief business officer previously stated in an interview with Reuter that a typical AI server has up to eight times the amount of DRAM and three times the amount of NAND that a normal server has.

• Continued Industry Focus on 3D DRAM

The DRAM market remains highly concentrated, currently dominated by key players such as Samsung Electronics, SK Hynix, and Micron Technology, collectively holding over 93% of the entire market share.

According to a report from TrendForce, as of the third quarter of 2023, Samsung leads the global market with a share of 38.9%, followed by SK Hynix (34.3%) and Micron Technology (22.8%).

Currently, 3D DRAM is in its early stages of development, with companies like Samsung actively joining the research and development battleground. The competition is intense as various players strive to lead in this rapidly growing market.

• Samsung: 4F2 DRAM

Since 2019, Samsung has been conducting research on 3D DRAM and announced the industry’s first 12-layer 3D-TSV (Through-Silicon Via) technology in October of the same year. In 2021, Samsung established a next-generation process development research team within its DS division, focusing on research in this field.

At the 2022 SAFE Forum, Samsung outlined the overall 3DIC journey of Samsung Foundry and indicated its readiness to address DRAM stacking issues with a logic-stacked chip, SAINT-D. The design aims to integrate eight HBM3 chips onto one massive interposer chip.

In May 2023, as per sources cited by “The Elec,” Samsung Electronics formed a development team within its semiconductor research center to mass-produce 4F2 structured DRAM.

The goal is reportedly to apply 4F2 to DRAM at 10nm processes or more advanced nodes, as DRAM cell scaling has reached its limit. The report suggests that if Samsung’s 4F2 DRAM storage unit structure research is successful, the chip die area can be reduced by around 30% compared to existing 6F2 DRAM storage unit structures without changing the node.

In October of the same year, at the “Memory Technology Day” event, Samsung Electronics announced its plans to introduce a new 3D structure in the next-generation 10-nanometer more advanced nodes DRAM, rather than the existing 2D planar structure. The aim of this project is to increase the production capacity of a chip by over 100G.

At the “VLSI Symposium” held in Japan last year, Samsung Electronics presented a paper containing research results on 3D DRAM and showcased detailed images of 3D DRAM as an actual semiconductor implementation.

According to a report by The Economic Times, Samsung Electronics recently announced the opening of a new R&D laboratory in Silicon Valley, USA, dedicated to the development of next-generation 3D DRAM.

The laboratory is operated under Silicon Valley’s Device Solutions America (DSA) and is responsible for overseeing Samsung’s semiconductor production in the United States, as well as focusing on the development of new generations of DRAM products.

• SK Hynix – Introducing IGZO as the Channel Material for Future DRAM

Per SK Hynix’s research, the IGZO channel is attracting attention to improve the refresh characteristics of DRAM.

Reportedly, IGZO thin film transistors have been used in the display industry for a long time due to their moderate carrier mobility, extremely low leakage current and substrate size scalability. It can be a candidate for a stackable channel material for future DRAM.

• NEO – 3D X-DRAM Offers 8x Density Boost

NEO Semiconductor, a US memory technology company, introduces its groundbreaking technology, 3D X-DRAM, aimed at overcoming the capacity limitations of DRAM.

3D X-DRAM features the first-ever array structure of DRAM units based on Floating Body Cell (FBC) technology, akin to 3D NAND. Similar to 3D NAND Flash, its logic involves stacking layers to increase memory capacity. The FBC technology in 3D NAND Flash enables the formation of a vertical structure with the addition of a layer mask, offering high yield, low cost, and a significant density boost.

According to Neo’s estimates, the 3D X-DRAM technology can achieve a density of 128 Gb across 230 layers, which is eight times the current density of DRAM. NEO proposes a target of an eightfold capacity increase every decade, aiming to achieve a capacity of 1Tb between 2030 and 2035, representing a 64-fold increase compared to the current core capacity of DRAM.

This expansion is intended to meet the growing demand for high-performance and large-capacity semiconductor storage, especially for AI applications like ChatGPT.

“3D X-DRAM will be the absolute future growth driver for the Semiconductor industry,” said Andy Hsu, Founder and CEO of NEO Semiconductor.

• Japanese Research Team: BBCube 3D Outperforms DDR5 by 30x

A research team at the Tokyo Institute of Technology in Japan has introduced a groundbreaking 3D DRAM stacking design technology called BBCube, which enables superior integration between processing units and DRAM.

The most significant aspect of BBCube 3D lies in achieving a three-dimensional connection between processing units and DRAM instead of the traditional two-dimensional linkages. The team employs an innovative stacking structure while using an innovative stacked structure in which the PU dies sit atop multiple layers of DRAM, all interconnected via through-silicon vias (TSVs).

The overall structure of BBCube 3D is compact, devoid of typical solder microbumps, and utilizes TSVs instead of longer wires, collectively contributing to achieving low parasitic capacitance and low resistance, thereby enhancing the electrical performance of the device in various aspects.

The research team evaluated the speed of the new architecture and compared it with two of the most advanced memory technologies, DDR5 and HBM2E. Researchers claim that BBCube 3D could potentially achieve a bandwidth of 1.6 terabytes per second, which is 30 times higher than DDR5 and 4 times higher than HBM2E.

Furthermore, due to features like low thermal resistance and low impedance in BBCube, potential thermal management and power issues associated with 3D integration could be mitigated. The new technology significantly improves bandwidth while consuming only 1/20 and 1/5 of the bit access energy compared to DDR5 and HBM2E, respectively.

• Conclusion

The evolution of DRAM technology from 1D to 2D and now to the diverse structures of 3D has offered the industry various solutions to address its challenges. However, optimizing and improving manufacturing costs, durability, and reliability remain significant challenges in advancing 3D DRAM technology. Due to the difficulties in developing new materials and physical limitations, the commercialization of 3D DRAM still requires some time.

Based on the current research progress, the industry is actively engaged in the development of 3D DRAM, which are still in the early stages. According to industry insiders, it is predicted that 3D DRAM will begin to emerge around 2025, with actual mass production becoming feasible after 2030.

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• Top 10 Foundries Experience 7.9% QoQ Growth in 3Q23, with a Continued Upward Trend Predicted for Q4, Says TrendForce

(Photo credit: Samsung)

Another breakthrough has emerged in flash memory layer technology! A recent report cited by tom’s Hardware has suggested that at the upcoming International Solid-State Circuits Conference (ISSCC) in February of this year, Samsung Electronics will unveil the next-generation V9 QLC NAND solution, pushing flash memory layer technology to 280 layers.

The Battle of Layers is Far from Over

Reportedly, Samsung’s V9 QLC boasts a storage density of 28.5Gb per square millimeter, achieving a maximum transfer rate of 3.2 Gbps. This surpasses the current leading QLC products (2.4 Gbps) and is poised to meet the requirements of future PCIe 6.0 solutions.

Additionally, the report further highlights that Samsung’s V9 QLC is considered the highest-density flash memory solution to date.

Before Samsung, major storage giants such as Micron and SK Hynix had already surpassed the 200-layer milestone. Micron reached 232 layers with a storage density of 19.5Gb per square millimeter, while SK Hynix achieved 238 layers with a storage density of 14.4Gb per square millimeter.

Still, 280 layers are not the end of the storage giants’ layer count competition; there will be breakthroughs with even higher layer counts in the future.

In August 2023, SK Hynix unveiled the world’s highest-layer 321-layer NAND flash memory samples, claimed to have become the industry’s first company developing NAND flash memory with over 300 layers, with plans for mass production by 2025.

Reportedly, SK Hynix’s 321-layer 1Tb TLC NAND achieves a 59% efficiency improvement compared to the previous generation 238-layer 512Gb. This is due to the ability to stack more units of data storage to higher levels, achieving greater storage capacity on the same chip, thereby increasing the output of chips per wafer unit.

On the other hand, Micron plans to introduce higher-layer products beyond the 232-layer milestone. Samsung, with ambitious plans, aims to stack V-NAND to over 1000 layers by 2030.

Kioxia and Western Digital, after showcasing their 218-layer technology in 2023 following the 162-layer milestone, also intend to develop 3D NAND products with over 300 layers in the future.

Amid Memory Market Rebound, What’s the Trend in NAND Flash Prices?

Amid economic headwinds and subdued demand in the consumer electronics market, the memory industry experienced a prolonged period of adjustment. It wasn’t until the fourth quarter of 2023 that the memory market began to rebound, leading to improved performances for related storage giants.

According to research conducted by TrendForce, a global market research firm, NAND Flash contract prices declined for four consecutive quarters starting from the third quarter of 2022, until they began to rise in the third quarter of 2023.

With a cautious outlook for market demand in 2024, the trend in NAND Flash prices will depend on the capacity utilization rates of suppliers.

TrendForce has projected a hike of 18-23% for NAND Flash contract prices, with a more moderated QoQ price increase of 3-8% for 2Q24. As the third quarter enters the traditional peak season, the quarterly price increase could potentially expand synchronously to 8-13%.

In 4Q24, the general price rally is anticipated to continue if suppliers maintain an effective strategy for controlling output. For NAND Flash products, their contract prices are forecasted to increase by 0-5% QoQ for 4Q24.

(Photo credit: Samsung)