DRAM Spot Price:

The spot market has yet to show a demand turnaround; and sellers, in particular Samsung, have increased the chip supply, thereby pushing prices back down again. Looking at different types of DRAM products, module houses and channels have relatively high inventory levels for DDR4 products. Hence, the downward pressure on spot prices of DDR4 products is greater compared with spot prices of DDR5 products. Overall, even though contract prices have again registered significant increases in 2Q24, this rally has no positive effect on spot prices. Instead, spot transactions continue to show declining quantity, and the downward price pressure has become more pronounced. The average spot price of mainstream chips (i.e., DDR4 1Gx8 2666MT/s) has dropped by 1.19% from US$1.940 last week to US$1.917 this week.

NAND Flash Spot Price:

The Chinese government’s cracking down on smuggling of memory products, as well as the persistently sluggish demand from the retail market, have prompted module houses to amplify their sales intensity to actively pursue transactions, which led to a loosening in prices. Without replenishment of orders within the retail market, together with how wafer prices have surged from rock bottom to nearly 80% by now, the depletion of spot prices could carry on in the near future. Spot price for 512Gb TLC wafers has dropped by 2.61% this week, arriving at US$3.579.

According to reports from Reuters, Investing.com, and other global news outlets, Matt Murphy, the CFO of Micron, stated on May 21st that the company’s capital expenditure forecast for 2024 is expected to reach approximately USD 8 billion, up from the previous estimate of USD 7.5 billion. This increase is primarily attributed to investments in High Bandwidth Memory (HBM).

Micron’s Chief Operating Officer, Manish Bhatia, stated that the scale of the HBM business is expected to expand to several billion dollars in the 2025 fiscal year.

As per a previous report by Economic Daily News, Micron’s current 8-layer stacking model offers the advantage of higher heat dissipation efficiency, as fewer layers allow for better cooling, ensuring stable chip performance. Additionally, Micron is planning to launch a 12-layer stacked 36Gb DRAM chip. Per a report from Tom’s Hardware, this new chip’s capacity is expected to be 50% greater than that of the previous 8-layer stack.

In March, Micron CEO Sanjay Mehrotra indicated that the company’s HBM earmarked for AI applications are sold out for 2024, with much of the 2025 supply already allocated.

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• [News] Micron Expects 4-6% Quarterly DRAM Supply Impact Post Taiwan Earthquake
• [News] Micron’s Financial Report Reveals High Demand for HBM in 2025, Capacity Nears Full Allocation

(Photo credit: Micron)

According to the latest quarterly analysis report from SEMI, a major microelectronics association, global silicon wafer shipments in the first quarter of 2024 reached 2,834 million square inches (MSI), marking a 5.4% decrease from the previous quarter and a 13.2% decrease from the same period last year.

SEMI attributes this decline in silicon wafer shipments to the continuing decline in IC fab utilization and inventory adjustments. Consequently, shipments of silicon wafers of all sizes experienced negative growth in the first quarter of 2024.

Industry sources cited by the same report note that, based on recent trends in foundry orders, apart from TSMC, other semiconductor manufacturers have seen capacity utilization rates around 70%. Among these, DRAM and Flash memory wafer shipments have shown year-on-year increases of 20.3% and 1%, respectively, indicating better performance compared to previous periods.

Japanese silicon wafer manufacturer Sumco recently announced in its financial report that in the first quarter, overall demand for 12-inch silicon wafers had bottomed out. Demand for logic chips used in AI and DRAM had increased. However, for applications outside of AI, customers continued to adjust their production.

Sumco estimates that due to customer production adjustments and the recovery of silicon wafer demand, it may take until the second half of 2024 for the situation to improve.

Industry sources cited by Economic Daily News believe that most IC design companies have returned to normal days of inventory (DOI) and are prioritizing urgent orders for foundries. However, the inventory levels of fabs and memory fabs remain historically high, so they will primarily focus on digesting existing long-term contracts (LTA) in the short term.

Read more

• [News] Silicon Wafer Long-Term Contracts Unstable, Major Foundry Seeks Price Cut from Japanese Suppliers

(Photo credit: TSMC)

According to its latest roadmap revealed at the company’s European Technology Symposium earlier, TSMC would now be able to more than quadruple its CoWoS capacity from 2023 levels by the end of 2026, the report indicated.

Last year, the foundry leader announced plans to more than double its CoWoS capacity by the end of 2024, but now it needs to be more ambitious, not only to meet existing demand but also address the future market.

TSMC is also preparing additional versions of CoWoS (specifically CoWoS-L) to support building system-in-packages (SiPs) with up to eight reticle sizes, just in case that increasing CoWoS capacity four-fold over three years may still be insufficient, the report said.

In addition to CoWoS, TSMC also plans to expand its system-on-integrated chips (SoIC) capacity at a CAGR of 100% through 2026, indicating that its SoIC capacity will increase eight-fold from 2023 levels by the end of 2026, according to AnandTech.

When it comes to the latest overseas expansion plans regarding major Taiwanese foundries, TSMC’s Kumamoto Fab 1, a joint investment between TSMC, Sony Semiconductor Solutions Corporation, and Denso Corporation, was inaugurated in February. Construction of the second Kumamoto fab is slated to begin by the end of 2024, with operations starting by the end of 2027.

UMC, Taiwan’s second-largest wafer foundry, announced on May 21st the arrival of the first equipment tools for phase 3 expansion at its Fab12i located in Singapore. According to a report by CNA, UMC anticipates the construction of the facility will be completed by mid-year. However, due to adjustments in customer orders, mass production has been delayed by six months to early 2026.

In October, 2023, Powerchip Semiconductor Manufacturing Corporation (PSMC), in collaboration with SBI Holdings, Inc., announced plans regarding its first semiconductor wafer plant in Japan, which is expected to be located in the Second Northern Sendai Central Industrial Park in Ohira Village, Kurokawa District, Miyagi Prefecture (Second Northern Sendai Central Industrial Park).

Previous reports indicated that PSMC plans to construct multiple plants, with the first phase potentially starting construction as early as 2024, involving an investment of around JPY 400 billion (USD 2.6 billion).

Read more

• [News] TSMC Reportedly Prepares Next-generation HBM4 Manufacturing, Utilizing 12nm and 5nm Process Nodes
• [News] TSMC’s Kumamoto Plant – Semiconductor Bubble or Once-in-a-Century Opportunity?

(Photo credit: TSMC)

It is expected that 20 brands will release 80 models featuring this processor. Combined shipments of Metro Lake and Lunar Lake this year are projected to reach 40 million units. Unlike the previous generation, Lunar Lake’s packaging design integrates LPDDR5x memory into a single package, emphasizing low power consumption.

On May 20th, Microsoft launched its next-generation AI PCs, equipped with a more powerful AI assistant, Copilot, and new features. It also established a new standard for AI PC architecture, “Copilot+ PC.” The initial products all feature Qualcomm’s “Snapdragon X Elite” processors designed with Arm architecture.

Qualcomm’s CPUs in the new PCs are equipped with a Neural Processing Engine (NPE) designed specifically for AI applications, boasting 45 TOPS. This, as per another report from the Economic Daily News, results in a 58% increase in speed and extended battery life compared to Apple’s latest top-tier MacBook, which uses the M3 chip. Additionally, they support Microsoft’s AI chatbot, Copilot.

Intel, on the other hand, made a rare announcement, revealing that its next-generation Lunar Lake will have a total performance exceeding 100 TOPS, with the NPU alone exceeding 45 TOPS—nearly three times that of the previous generation. Additionally, the CPU and GPU combined computing power will exceed 60 TOPS, making it the second qualified processor for Microsoft’s Copilot+ PC platform.

However, it is important to note that according to Intel’s plans, the new generation processors Ultra 5/7/9 will be bundled with memory and shipped together with the CPU. Specifically, the high-end Ultra 9 will be bundled with 32GB of memory, while the Ultra 5 and Ultra 7 will have 16GB and 32GB versions. Per Microsoft’s recommendations, AI PCs need at least 16GB of memory. While Intel’s approach meets this requirement, it limits the ability of brands to adjust specifications and leaves memory manufacturers out of the loop.

In simpler terms, there is still a demand for 8GB memory in lower-end notebooks, and high-end laptops can require more than 64GB of memory. However, Intel’s Lunar Lake constraints make it difficult to plan both high-end and entry-level versions. Industry sources cited in the same report from Economic Daily News indicate that Intel’s next-generation Arrow Lake will not be bundled with memory.

Reportedly, industry sources also state that procurement contracts with memory suppliers have traditionally been long-term, accounting for annual memory requirements. Now, Intel’s bundling of memory with its single platform changes the industry’s ecosystem. Previously, PC brands would develop various combinations (CPU + memory + SSD capacity) for their product lines. However, with Intel defining five laptop CPU + memory specifications, it limits the customization capabilities of PC brands.

With Intel launching Lunar Lake early, AMD is set to counter with its next-generation AI processor Ryzen series named Strix Point in the fourth quarter. The Strix Point processor will feature AI processing power exceeding 50 TOPS, and there will also be an APU, Strix Halo, expected to launch around the end of the year with performance exceeding 60 TOPS, making it a significant player in AI computing power.

CEO Pat Gelsinger recently demonstrated the performance of the Lunar Lake processor, emphasizing that its total AI workload exceeds 100 TOPS, with the NPU contributing 45 TOPS. The CPU features Lion Cove architecture P-cores and Skymont architecture E-cores, while the GPU and CPU together provide over 60 TOPS of computing power. This means Intel’s chip AI performance will be more than three times that of current products, with a total combined performance exceeding 100 TOPS.

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• [News] Battle in AI PCs: Exploring Intel, AMD, and Qualcomm Chips’ AI Computing Power
• [News] AMD Hosts Innovation Summit, CEO Lisa Su Highlights the Beginning of AIPC Era

(Photo credit: Intel)

The report notes that in recent years, many data centers have been established in Nordic countries due to the cool climate, tax incentives, and ample supply of renewable energy. Finland’s wind power capacity has seen significant growth over these years, up by 75% to 5,677 megawatts by 2022, which brings electricity prices even down to negative values on particularly windy days.

Thus, Data center operators like Google have been taken advantage of this renewable energy, and already signed long-term wind power purchase agreements in Finland.

Driven by the AI wave, cloud providers such as Microsoft, Google, Meta, and Amazon have an increasingly robust demand for AI servers and data centers.

According to a previous forecast by TrendForce, considering the global CSPs’ demands for high-end AI servers (Those equipped with NVIDIA, AMD, or other high-end ASIC chips included) in 2024, the demands from four major U.S. CSPs: Microsoft, Google, AWS, and Meta are expected to account for 20.2%, 16.6%, 16%, and 10.8% of global demand respectively, reigning over the global market with a total proportion of more than 60%.

Read more

• [Insights] Big Four CSPs Continue to Shine in Q1 2024 Financial Reports, AI Returns Garnering Attention

(Photo credit: Google)

Young Hyun Jun initially joined Samsung Electronics in 2000, focusing on the development and strategic marketing of DRAM and flash memory. He has been in charge of the memory business since 2014, served as CEO of Samsung SDI, the battery division, in 2017, and led the Future Business Division starting in 2024.

In the press release, Samsung expressed confidence that Young Hyun Jun will strengthen its competitiveness amid an uncertain global business environment.

Upon approval by the board of directors and shareholders, Young Hyun Jun will also be appointed as CEO of Samsung. Samsung employs a dual CEO system, with one CEO responsible for the semiconductor division and the other for the device experience division, which includes the mobile and visual display business groups.

At the time of this personnel announcement, Samsung is striving to catch up with its competitor SK Hynix in the AI memory sector. SK Hynix currently leads the market for high bandwidth memory (HBM), a crucial component for AI computing. SK Hynix previously stated that its HBM production capacity for this year and next year is already sold out.

TrendForce has analyzed that the current HBM3 supply for NVIDIA’s H100 solution is primarily met by SK hynix, leading to a supply shortfall in meeting burgeoning AI market demands. Samsung’s entry into NVIDIA’s supply chain with its 1Znm HBM3 products in late 2023, though initially minor, signifies its breakthrough in this segment.

Whether Samsung, led by Young Hyun Jun with his extensive memory experience, can regain ground in its competition with SK Hynix is under close observation.

Per a report from Reuters, a source has noted that since Samsung’s personnel changes typically occur at the beginning of the year, it is unusual to replace a high-ranking executive like this in the middle of the year.

Read more

• [News] HBM Boom May Lead to DRAM Shortages in the Second Half of the Year
• [News] Samsung Reportedly to Challenge Apple/TSMC with 3nm Exynos W1000

(Photo credit: Samsung)

According to TrendForce, the three largest DRAM suppliers are increasing wafer input for advanced processes. Following a rise in memory contract prices, companies have boosted their capital investments, with capacity expansion focusing on the second half of this year. It is expected that wafer input for 1alpha nm and above processes will account for approximately 40% of total DRAM wafer input by the end of the year.

HBM production will be prioritized due to its profitability and increasing demand. Regarding the latest developments in HBM, TrendForce indicates that HBM3e will become the market mainstream this year, with shipments concentrated in the second half of the year.

Currently, SK Hynix remains the primary supplier, along with Micron, both utilizing 1beta nm processes and already shipping to NVIDIA. Samsung, using a 1alpha nm process, is expected to complete qualification in the second quarter and begin deliveries mid-year.

The growing content per unit in PCs, servers, and smartphones is driving up the consumption of advanced process capacity each quarter. Servers, in particular, are seeing the highest capacity increase—primarily driven by AI servers with content of 1.75 TB per unit. With the mass production of new platforms like Intel’s Sapphire Rapids and AMD’s Genoa, which require DDR5 memory, DDR5 penetration is expected to exceed 50% by the end of the year.

As HBM3e shipments are expected to be concentrated in the second half of the year—coinciding with the peak season for memory demand—market demand for DDR5 and LPDDR5(X) is also expected to increase. With a higher proportion of wafer input allocated to HBM production, the output of advanced processes will be limited. Consequently, capacity allocation in the second half of the year will be crucial in determining whether supply can meet demand.

Samsung expects existing facilities to be fully utilized by the end of 2024. The new P4L plant is slated for completion in 2025, and the Line 15 facility will undergo a process transition from 1Y nm to 1beta nm and above.

The capacity of SK Hynix’s M16 plant is expected to expand next year, while the M15X plant is also planned for completion in 2025, with mass production starting at the end of next year.

Micron’s facility in Taiwan will return to full capacity next year, with future expansions focused on the US. The Boise facility is expected to be completed in 2025, with equipment installations following and mass production planned for 2026.

With the expected volume production of NVIDIA’s GB200 in 2025, featuring HBM3e with 192/384GB specifications, HBM output is anticipated to nearly double. Each major manufacturer will invest in HBM4 development, prioritizing HBM in their capacity planning. Consequently, due to capacity crowding effects, there may be shortages in DRAM supply.

Read more

• HBM3e Production Surge Expected to Make Up 35% of Advanced Process Wafer Input by End of 2024, Says TrendForce
• [News] DRAM Price Surge Halts, Could HBM Demand Drive Price Increases?

(Photo credit: Samsung)

Sources quoted by the reports indicated that Samsung has implemented an internal strategy called “Nemo,” specifically targeting NVIDIA. Its foundry now plans to commence mass production of the 3nm GAA process in the first half of 2024. The GAA technology is expected to overcome significant bottlenecks associated with the previous FinFET processes, but it is still uncertain if this will be sufficient to persuade NVIDIA.

NVIDIA has been cooperating with TSMC in advanced process nodes for developing its GPUs for quite a while, both in consumer and data center markets. The tech giant’s latest GPU families, including Ada Lovelace, Hopper, and Blackwell, are all manufactured using TSMC’s 5nm (4N) processes, according to the aforementioned reports.

It’s important to note that NVIDIA last used Samsung’s 8nm process for its GeForce RTX 30 “Ampere” GPUs, designed for the gaming segment. However, the successor to Ampere, the Ada Lovelace “GeForce RTX 40,” switched to TSMC’s 5nm process.

Considering the high demand for NVIDIA’s GPUs, the chipmaker is expected to procure chips from multiple semiconductor fabs, which is simliar to its previous strategy of dual-sourcing HBM and packaging materials, according to Wccftech.

(Photo credit: Samsung)

The emerging AI company Astera Labs has surpassed a market value of USD 10 billion and is renowned for providing high-speed transmission interface solutions for AI servers. Founded in 2017, the company celebrated its new public listing on NASDAQ this March.

Per a report from Business Today, the company, headquartered in California, USA, specializes in Retimer chips used for transmission in cloud data centers. These chips mitigate electronic signal attenuation issues, making them widely adopted in the market following PCIe Gen 5.

In response to the rapid expansion of the AI server market, Astera Labs is following in NVIDIA’s footsteps by establishing an R&D center, the Cloud-Scale Interop Lab, in Taiwan.

• • [COMPUTEX 2024] The Rise of Generative AI Sparks Innovation across Industries, with Taiwan-based Companies Leading as Essential Partners in the Global Supply Chain

(Photo credit: Astera Labs)