1. China’s EDA Industry into Fast Development with Efforts of Downstream Industries, Capital and Policies Propel

Within the broader context of China’s push for semiconductor self-sufficiency in recent years, the domestic EDA (Electronic Design Automation) industry in China has undergone remarkable growth. This growth has been spurred by a collaborative effort involving the Chinese government (through policies and investment funds), the expansion of the IC design sector (the growth of IC design scale and investments upstream and downstream), and private offered funds.

EDA companies in China are in rapid growth, and finance companies reached its zenith in 2021, with funding amounts consistently setting new records year after year. In 2022, EDA financing amounted to approximately 8 billion RMB, with companies like Primarius Technologies, Empyrean Technology, and Semitronix making their debut on the stock market. Over the past three years, these companies have sustained a continuous uptrend in their revenues. All in all, with support from various quarters, China’s EDA industry is now on a fast track to development.

2. Point Tools Take Center Stage for Chinese EDA Companies

Nowadays, the supply of EDA tools is largely controlled by Synopsys, Cadence, and Siemens EDA, three major players with deep technical expertise across the entire spectrum of EDA tools. While Empyrean Technology, having entered the arena early, boasts a comprehensive suite of EDA tools for analog circuit design and FPD, the majority of other Chinese EDA firms are strategically focusing on specialized point tools in simulation and verification.

These companies win customer recognition and purchases before broadening their path to other tool categories. Another strategic avenue pursued by Chinese EDA companies is the exploration of innovative opportunities in emerging fields such as AI chips, setting them apart from their larger counterparts.

3. China’s EDA Industry Enters a Phase of Consolidation, Confronting Challenges of Inexperience and Political Risks

Over the past few years, the number of Chinese EDA companies and the scale of funding have surged dramatically. As they experience rapid growth, mergers and acquisitions (M&A) and investments have become indispensable means for Chinese EDA firms to fortify their positions. This trend is becoming increasingly conspicuous, with a total of 20 M&A and investment deals occurring within the Chinese EDA sectors over the past three years, comprising 2 in 2021, 15 in 2022, and 3 in the first half of 2023.

Primarius Technologies (with 9 deals), Empyrean Technology (with 3 deals), and Univesta (with 4 deals, one of which was unsuccessful) are among the firms with comparatively high M&A activity. Beyond M&A and investment, Chinese EDA companies are accelerating their collaborations to achieve complementary advantages, a trend that is expected to continue to gain momentum in the future.

China’s EDA companies do encounter certain challenges during the integration process: (1) They lack prior experience in M&A and must continually learn and experiment. (2) Given the global semiconductor industry’s shifting dynamics, they may encounter obstacles from local governments when pursuing overseas M&A and investments.

As applications like AIGC, 8K, AR/MR, and others continue to develop, 3D IC stacking and heterogeneous integration of chiplet have become the primary solutions to meet future high-performance computing demands and extend Moore’s Law.

Major companies like TSMC and Intel have been expanding their investments in heterogeneous integration manufacturing and related research and development in recent years. Additionally, leading EDA company Cadence has taken the industry lead by introducing the “Integrity 3D-IC” platform, an integrated solution for design planning, realization, and system analysis simulation tools, marking a significant step towards 3D chip stacking.

Differences between 2.5D and 3D Packaging

The main difference between 2.5D and 3D packaging technologies lies in the stacking method. 2.5D packaging involves stacking chips one by one on an interposer or connecting them through silicon bridges, primarily used for assembling logic processing chips and high-bandwidth memory. On the other hand, 3D packaging is a technology that vertically stacks chips, mainly targeting high-performance logic chips and SoC manufacturing.

CPU and HBM Stacking Demands

With the rapid development of applications like AIGC, AR/VR, and 8K, it is expected that a significant amount of computational demand will arise, particularly driving the need for parallel computing systems capable of processing big data in a short time. To overcome the bandwidth limitations of DDR SDRAM and further enhance parallel computing performance, the industry has been increasingly adopting High-Bandwidth Memory (HBM). This trend has led to a shift from the traditional “CPU + memory (such as DDR4)” architecture to the “Chip + HBM stacking” 2.5D architecture. With continuous growth in computational demand, the future may see the integration of CPU, GPU, or SoC through 3D stacking.

3D Stacking with HBM Prevails, but CPU Stacking Lags Behind

HBM was introduced in 2013 as a 3D stacked architecture for high-performance SDRAM. Over time, the stacking of multiple layers of HBM has become widespread in packaging, while the stacking of CPUs/GPUs has not seen significant progress.

The main reasons for this disparity can be attributed to three factors: 1. Thermal conduction, 2. Thermal stress, and 3. IC design. First, 3D stacking has historically performed poorly in terms of thermal conduction, which is why it is primarily used in memory stacking, as memory operations generate much less heat than logic operations. As a result, the thermal conduction issues faced by current memory stacking products can be largely disregarded.

Second, thermal stress issues arise from the mismatch in coefficients of thermal expansion (CTE) between materials and the introduction of stress from thinning the chips and introducing metal layers. The complex stress distribution in stacked structures has a significant negative impact on product reliability.

Finally, IC design challenges from a lack of EDA tools, as traditional CAD tools are inadequate for handling 3D design rules. Developers must create their own tools to address process requirements, and the complex design of 3D packaging further increases the design, manufacturing, and testing costs.

How EDA Companies Offer Solutions

Cadence, during the LIVE Taiwan 2023 user annual conference, highlighted its years of effort in developing solutions. They have introduced tools like the Clarity 3D solver, Celsius thermal solver, and Sigrity Signal and Power Integrity, which can address thermal conduction and thermal stress simulation issues. When combined with Cadence’s comprehensive EDA tools, these offerings contribute to the growth of the “Integrity 3D-IC” platform, aiding in the development of 3D IC design.

“3D IC” represents a critical design trend in semiconductor development. However, it presents greater challenges and complexity than other projects. In addition to the challenges in Logic IC design, there is a need for analog and multi-physics simulations. Therefore, cross-platform design tools are indispensable. The tools provided by EDA leader Cadence are expected to strengthen the 3D IC design tool platform, reducing the technological barriers for stacking CPU, GPU, or SoC to enhance chip computing performance.

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC)

According to TrendForce’s latest investigation, Chinese foundries have already suspended plans to expand production capacity for advanced processes after the US government began restricting the exportation of equipment and technical support for processes related to non-planar architectures. TrendForce believes that a further tightening of the restrictions on lithography equipment will mainly affect mature processes, especially the 28nm. Chinese foundries might proceed more slowly in adding new production capacity or raising output for the 28nm process due to the prolonged reviews on their equipment purchases.

TrendForce semiconductor analyst, Joanne Chiao, said that Chinese semiconductor companies have already suspended the development of chips featuring the GAA architecture (i.e., nodes that are generally ≤3nm) after the US government began restricting the exportation of EDA tools and related technical support. If we talk about the FinFET architecture that Chinese foundries are able to produce for now, it is possible to achieve the faster computing speed of the more advanced chips by combining multiple lower-end chips. However, it might also be very challenging to raise the production yield rate of a solution that integrates multiple chips, not to mention that the power consumption of such solution might be very high as well.

Seeing the US export control, for now, US government has not imposed restrictions on the exportation of technical support for processes related to planar architectures. On the other hand, Chinese foundries might halt their advanced chip (14nm) production at any time if they encounter an equipment malfunction or another problem that requires technical support from US equipment providers.

At last, Chiao emphasized that the US sanction has definitely accelerated the development of an “all-China” semiconductor manufacturing supply chain. Nevertheless, the world’s top eight semiconductor equipment providers all come from Japan or the US. From the perspective of the foundry industry, it will be hard for China to realize a wholly or mostly native semiconductor supply chain within the foreseeable future.

According to TrendForce, as the United States continues to expand the content of various lists, successively pass anti-China bills, and explicitly prohibit the export of certain products to China, the two countries have gradually drifted apart and this antagonistic relationship will continue if no drastic changes occur between the two parties in the next 6-8 years.

In the face of U.S. encroachment, all sectors in China must continue to look for escape routes if the country wishes to tear down the many walls built by the U.S. and move towards industrial autonomy. China’s top priority is to make breakthroughs in the semiconductor field. As far as current development is concerned, there are still many companies in China’s domestic IC design industry moving towards advanced manufacturing processes even after leading manufacturers such as Huawei, Changsha Jingjia Microelectronics, and Goke Microelectronics were placed on the entity list. At the same time, semiconductor manufacturers such as SMIC, CXMT, and Yangtze Memory Technologies have repeatedly developed advanced process technologies while Hua Hong Group has gradually expanded in the field of mature processes. If this trend continues, it will not be difficult for China to realize semiconductor autonomy in processes above 10nm.

If U.S. effectively enforces EDA ban and does not expand controls, impact on China will emerge in 2025

The U.S. Department of Commerce’s export restrictions on Chinese manufacturers are escalating but the autonomy of China’s domestic semiconductor industry is also gradually increasing. As the confrontation between the United States and China intensifies, the United States has launched a new wave of export control measures. On August 12, 2022, the U.S. Department of Commerce announced that it will restrict the export to China of EDA software required to design integrated circuits with GAAFET structure. Since GAAFET is a structure that is used in processes below 3nm, this move is equivalent to setting an advanced threshold for China’s semiconductor development.

Domestic Chinese IC designers who are committed to the development of SoCs, cloud computing chips, and GPUs are destined to move to more advanced manufacturing processes in order to meet the iterative needs of product upgrades and are expected to move toward the 4nm manufacturing process in the next 2 to 4 years. If the U.S. effectively implements the EDA software ban and does not expand the scope of EDA software restrictions, the impact of the ban on China’s semiconductor industry is expected to gradually emerge in 2025, not only delaying the development schedule of some domestic Chinese IC designers but even causing developmental stagnation.

（Image credit: Pixabay）

Although current semiconductor process technologies have evolved to the 3nm and 5nm nodes, SoC (system on a chip) architecture has yet to be manufactured at these nodes, as memory and RF front-end chiplets are yet to reach sufficient advancements in transistor gate length and data transmission performance. Fortunately, EDA companies are now attempting to leverage heterogeneous integration packaging technologies to link the upstream and downstream semiconductor supply chains as well as various IP cores. Thanks to this effort, advanced packaging technologies, including 2.5D/3D IC and SiP, will likely continue to push the limits of Moore’s Law.

While SoC development has encountered bottlenecks, EDA tools are the key to heterogeneous integration packaging

As semiconductor process technologies continue to evolve, the gate length of transistors have also progressed from μm (micrometer) nodes to nm (nanometer) nodes. However, the more advanced process technologies are not suited for manufacturing all semiconductor components, meaning the development of SoC architectures has been limited as a result. For instance, due to physical limitations, memory products such as DRAM and SRAM are mostly manufactured at the 16nm node at the moment. In addition, RF front-end chiplets, such as modems, PA (power amplifiers), and LNA (low noise amplifiers) are also primarily manufactured at the 16nm node or other μm nodes in consideration of their required stability with respect to signal reception/transmission.

On the whole, the aforementioned memory, and other semiconductor components cannot be easily manufactured with the same process technologies as those used for high-end processors (which are manufactured at the 5nm and 3nm nodes, among others). Hence, as the current crop of SoCs is not yet manufactured with advanced processes, EDA companies including Cadence, Synopsys, and Siemens (formerly Mentor) have released their own heterogeneous integration packaging technologies, such as 2.5D/3D IC and SiP (system in package), in order to address the demand for high-end AI, SoC architecture, HPC (high performance computing), and optical communication applications.

EDA companies drive forward heterogeneous integration packaging as core packaging architecture and integrate upstream/downstream supply chain

Although the current crop of high-end semiconductor process technologies is still incapable of integrating such components as memory, RF front-end, and processors through an SoC architecture, as EDA companies continue to adopt heterogeneous integration packaging technology, advanced packaging technologies, including 2.5D/3D IC and SiP, will likely extend the developmental limitations of Moore’s Law.

Information presented during Semicon Taiwan 2021 shows that EDA companies are basing their heterogeneous integration strategies mainly on the connection between upstream and downstream parts of the semiconductor supply chain, in addition to meeting their goals through chip packaging architectures. At the moment, significant breakthroughs in packaging technology design and architecture remain unfeasible through architectural improvements exclusively. Instead, companies must integrate their upstream chip design and power output with downstream substrate signal transmission and heat dissipation, as well as other factors such as system software and use case planning. Only by integrating the above factors and performing the necessary data analysis can EDA companies gradually evolve towards an optimal packaging architecture and in turn bridge the gap of SoC architectures.

With regards to automobiles (including ICE vehicles and EVs), their autonomous driving systems, electronic systems, and infotainment systems require numerous and diverse semiconductor key components that range from high-end computing chips to mid-range and entry-level MCUs. As such, automotive chip design companies must carefully evaluate their entire supply chain in designing automotive chip packages, from upstream manufacturers to downstream suppliers of substrates and system software, while also keeping a holistic perspective of various use cases. Only by taking these factors into account will chip design companies be able to respond the demands of the market with the appropriate package architectures．

（Image credit: Pexels）