With the semiconductor market facing uncertainties and limited signs of industry recovery in the first half of 2024, foundries in China, Taiwan, and South Korea are all implementing price reductions to secure orders and solidify customer relationships.

According to TechNews citing from supply chain sources, Samsung Foundry, which had not taken action previously, is expected to follow suit with price cuts in the first quarter to keep pace with competitors.

Reportedly, industry sources suggest that Samsung Foundry is adopting a price reduction strategy in the first quarter of 2024, offering discounts ranging from 5% to 15% and expressing a willingness to negotiate.

Samsung Foundry’s actions can be interpreted as a goodwill gesture towards its customers. The company has been in constant competition with TSMC, especially in processes below 5nm, and actively engaging in negotiations with customers, seeking collaboration opportunities with Qualcomm, NVIDIA, AMD and others.

Considering the subdued semiconductor market in 2023, fabs in both China and South Korea have implemented price cuts to secure orders. The price reductions for mature processes in 8-inch and 12-inch wafer reached 20-30%, while Taiwanese fabs have also made concessions in pricing.

TSMC, the leading foundry, had already been reported to offer price concessions in 2023, with the major focus on mask costs rather than foundry services. It was mentioned at that time that TSMC’s price concessions primarily applied to the 7nm process, where utilization rates were lower, and the extent of concessions depended on the volume of orders from customers.

In terms of the global foundry landscape, according to data published by TrendForce, Taiwan holds approximately 46% of global foundry capacity, followed by China (26%), South Korea (12%), the US (6%), and Japan (2%).

However, due to government incentives and subsidies promoting local production in countries like China and the US, the semiconductor production capacities of Taiwan and South Korea are projected to decrease to 41% and 10%, respectively, by 2027.

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(Photo credit: Samsung)

Taiwanese Semiconductor testing and packaging giant ASE announced today that its subsidiary, ASE Semiconductor, will lease the plant in Nanzih, Kaohsiung, owned by Taiwan’s ASE Test Inc., to expand its packaging capacity.

In the announcement, ASE Holdings revealed that ASE Semiconductor would lease a plant in Nanzih District, Kaohsiung, from its subsidiary ASE Test Inc. The total floor area of the building is approximately 15,600 square meters, with an estimated total usage rights asset value of NTD 742 million (approximately USD 23.8 million).

ASE Holdings stated that the primary purpose of this move is to optimize the overall planning and efficient utilization of plant space within the group, as well as to expand ASE’s packaging capacity.

According to CNA’s report, industry sources believe that ASE’s primary objective with this expansion is to enhance its production capacity for advanced packaging of Artificial Intelligence (AI) chips, but it is not directly related to CoWoS packaging.

Market insiders point out that ASE Holdings has been collaborating with foundry on technologies related to advanced packaging interposers and has CoWoS solutions. The earliest expected time for mass production is by the end of this year or early next year.

Reportedly, according to data, ASE’s Kaohsiung plant contributes to approximately 20% of ASE Holding’s overall revenue. The plant primarily provides services such as packaging, wafer bumping and probing, materials, and final testing.

The Kaohsiung plant is also establishing several smart plants, focusing on high-end processes, including Fan-Out packaging, System-in-Package (SiP), wafer bumping, and FlipChip packaging. These technologies find applications in various fields, including automotive, medical, IoT, high-speed computing, artificial intelligence, and application processors.

ASE actively positions itself in various advanced packaging technologies. Notably, the Fan-Out Chip on Substrate with Bridge (FOCoS-Bridge) packaging technology integrates multiple Application-Specific Integrated Circuits (ASICs) and High Bandwidth Memory (HBM), targeting the customized AI chip advanced packaging market.

In addition, ASE Semiconductor has introduced a cross-platform integrated design tool that combines several advanced packaging technologies, addressing the demands of advanced packaging for AI chips.

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(Photo credit: ASE)

Intel CEO Pat Gelsinger has discussed around Intel’s process status, comparisons with TSMC in a recent interview. According to Barron’s report, Gelsinger mentioned in the interview that Intel’s 18A process and TSMC’s N2 process seem comparable, with no significant advantage for either of them.

However, Gelsinger claimed that, ‘But the backside power delivery, everybody says Intel, score.’ He further stated, ‘it gives better area efficiency for silicon, which means lower cost. It gives better power delivery, which means higher performance.’

Gelsinger mentioned that good transistor and great power delivery make 18A a little bit ahead of N2. Besides, TSMC has given a very high-cost envelope, where Intel can fit underneath to be margin accretive.

In fact, not only TSMC and Intel, but also including Samsung, the three semiconductor manufacturing giants are actively positioning themselves in the increasingly competitive field of advanced process technology.

At the recent IEEE International Electron Devices Meeting (IEDM), Intel, TSMC, and Samsung each showcased their CFET (Complementary FET) transistor solutions. The stacked CFET transistor architecture involves stacking two types of transistor -nFETs and pFETs- together, aiming to replace Gate-All-Around (GAA) and become the next-generation transistor design for doubling density.

As reported by IEEE Spectrum, Intel was the first foundry to showcase the CFET solution, publicly unveiling an early version back in 2020. During the conference, Intel introduced one of the simplest circuits manufactured with CFET, focusing on improvements for an inverter.

The CMOS inverter sends the same input voltage to the gates of two-transistor stacked together, generating an output that is logically opposite to the input, and the inverter is completed on a single fin.

Intel also improved the CFET stack’s electrical characteristics by increasing the number of nanosheets per device from two to three, decreasing the separation between the two devices from 50 nm to 30 nm.

According to the current progress, experts, as indicated by IEEE Spectrum, anticipate that the commercialization of CFET technology on a large scale will likely take another 7 to 10 years from now. Before reaching that stage, there are still many preparatory tasks that need to be completed.

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(Photo credit: Intel)

An increasing number of Chinese semiconductor design companies are seeking collaboration with testing and packaging facilities in Malaysia to carry out advanced chip packaging. According to Reuters’ report, this move aims to hedge the risk of potential expanded U.S. restrictions on the Chinese semiconductor industry.

As there is currently only one non-U.S. testing and packaging provider in Malaysia with advanced capabilities, namely ASE Technology Holding Co., a Taiwanese semiconductor packaging and testing firm, industry sources believe that ASE is likely to become the top choice for orders from Chinese enterprises.

Previously, the U.S. has imposed controls on China’s advanced semiconductor manufacturing processes and access to high-performance chips from major companies like NVIDIA. However, advanced packaging has not yet fallen within the restricted scope.

Two anonymous sources reportedly revealed that some of the Chinese businesses are showing interest in advanced chip packaging services. Despite the fact that the chip packaging sector has not yet faced export controls from the U.S., concerns are rising among businesses due to its involvement in sophisticated technology, fearing that it might be targeted for curbs on exports in the future.

Reuters’ report also indicates that due to the relatively affordable investment costs in Malaysia and the availability of experienced workforce and sophisticated equipment, an increasing number of Chinese chip design firms are seeking Malaysian Firms to carry out advanced chip packaging activities, including graphic processing units (GPUs).

Insiders have informed Reuters that the related contracts only involve packaging and do not violate any restrictions imposed by the U.S.. Additionally, they clarified that wafer manufacturing is not included in these contracts.

Two of the sources mentioned that some contracts have already been agreed. However, these insiders prefer not to disclose the names of the involved companies.

Meanwhile, according to a report from Taiwan’s Economic Daily News, when observing the global landscape of advanced packaging, in addition to TSMC, there are integrated device manufacturers (IDMs) like Intel and Samsung, as well as outsourcing semiconductor assembly and test (OSAT) companies like ASE Technology, Amkor, and others that possess advanced packaging capabilities. Among them, only ASE Technology, Amkor, and Intel have production capacity in Malaysia.

Reportedly, industry analysts predict that Chinese companies seeking advanced packaging support in Malaysia, due to geopolitical considerations, are likely to avoid American companies such as Intel and Amkor. Given that ASE is not an American company and can provide high-end packaging services, it is expected to be the preferred choice for Chinese companies.

ASE has previously stated that it will continue to invest in advanced packaging for AI, expecting the performance of advanced packaging to double next year compared to this year.

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(Photo credit: ASE Holdings)

Following Intel’s move to split its outsourced foundry model, TSMC is gearing up to expand its advanced manufacturing processes in Taiwan, ready to face the competition head-on.

According to China Time’s report, following the equipment first tool-in at the 2nm fab in Baoshan scheduled for April next year, industry sources suggest a high likelihood of the 1.4nm fab being established in the second phase of the Central Taiwan Science Park.

Additionally, TSMC is actively expanding its CoWoS process and considering the construction of its 7th advanced packaging and testing plant in the central region, with Chiayi Science Park and Yunlin actively under consideration.

Semiconductor industry insiders point out that TSMC is beginning to feel the pressure, and this year, founder Morris Chang’s main concern regarding competition has shifted from Samsung to the resurgent Intel.

Starting from the second quarter of next year, Intel, a rival of TSMC, plans to separately disclose financial reports for chip development and Intel Foundry Services (IFS), implementing its internal foundry outsourcing model.

Intel’s move aims to protect the assets and know-how of third-party customers. Coupled with international chip design firms gradually releasing orders to Intel due to diversified supply chain concerns, it shows that Intel’s outsourcing strategy is gradually proving effective.

Intel’s recent successes in foundry processes, including the PowerVia backside power delivery technology, glass substrates and Foveros Direct for advanced packaging.

According to TrendForce’s 3Q23 Ranking of  Global Top10 Foundries by Revenue, Intel’s foundry business has entered the global top 10 for the first time, ranking ninth with the industry’s fastest quarterly growth.

Confronted with growing competition from Intel, TSMC is intensifying its efforts and accelerating the construction of advanced process production capacity. The recent expansion plans are becoming clearer, with the 1.4nm fab likely located in the second phase of the Central Taiwan Science Park, aligning with the ongoing increase in demand for advanced packaging.

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(Photo credit: TSMC)