According to reports from Korean news outlet FN News and Wccftech, aiming to win back NVDIA as a major customer, Samsung has made it a priority to secure chip order from the GPU heavyweight this year. To achieve this, Samsung is reportedly doing everything possible to ensure the company’s 3nm process node, which uses GAA (Gate-All-Around) architecture, meets NVIDIA’s requirements.

Sources quoted by the reports indicated that Samsung has implemented an internal strategy called “Nemo,” specifically targeting NVIDIA. Its foundry now plans to commence mass production of the 3nm GAA process in the first half of 2024. The GAA technology is expected to overcome significant bottlenecks associated with the previous FinFET processes, but it is still uncertain if this will be sufficient to persuade NVIDIA.

NVIDIA has been cooperating with TSMC in advanced process nodes for developing its GPUs for quite a while, both in consumer and data center markets. The tech giant’s latest GPU families, including Ada Lovelace, Hopper, and Blackwell, are all manufactured using TSMC’s 5nm (4N) processes, according to the aforementioned reports.

It’s important to note that NVIDIA last used Samsung’s 8nm process for its GeForce RTX 30 “Ampere” GPUs, designed for the gaming segment. However, the successor to Ampere, the Ada Lovelace “GeForce RTX 40,” switched to TSMC’s 5nm process.

Considering the high demand for NVIDIA’s GPUs, the chipmaker is expected to procure chips from multiple semiconductor fabs, which is simliar to its previous strategy of dual-sourcing HBM and packaging materials, according to Wccftech.

(Photo credit: Samsung)

Astera Labs, a leading provider of AI server connectivity solutions, has announced that it will gather Taiwanese manufacturers to establish its first Cloud-Scale Interop Lab outside of Silicon Valley in Taiwan. According to a report from Commercial Times, the company will closely collaborate with major Taiwanese ODM clients, while key manufacturers such as Quanta, Inventec, Wistron, Wiwynn, and Foxconn are expected to benefit from this initiative.

The emerging AI company Astera Labs has surpassed a market value of USD 10 billion and is renowned for providing high-speed transmission interface solutions for AI servers. Founded in 2017, the company celebrated its new public listing on NASDAQ this March.

Per a report from Business Today, the company, headquartered in California, USA, specializes in Retimer chips used for transmission in cloud data centers. These chips mitigate electronic signal attenuation issues, making them widely adopted in the market following PCIe Gen 5.

In response to the rapid expansion of the AI server market, Astera Labs is following in NVIDIA’s footsteps by establishing an R&D center, the Cloud-Scale Interop Lab, in Taiwan.

• • [COMPUTEX 2024] The Rise of Generative AI Sparks Innovation across Industries, with Taiwan-based Companies Leading as Essential Partners in the Global Supply Chain

(Photo credit: Astera Labs)

As AI-related semiconductors has been driving the demand of High Bandwidth Memory (HBM), the NAND flash market now also feels the vibe. According to industry sources cited by Business Korea, the NAND Flash market competition is intensifying, while memory giants Samsung and SK Hynix are ramping up their efforts to improve the performance and capacity of NAND products.

In April, Samsung confirmed that it has begun mass production for its one-terabit (Tb) triple-level cell (TLC) 9th-generation vertical NAND (V-NAND), boasted to improve the bit density by about 50% compared to the 8th-generation V-NAND, with the number of layers reaching 290, according an earlier report by The Korea Economic Daily.

Based on the report on May 20 by Business Korea, Samsung intends to dominate the AI SSD market with its 9th Generation V-NAND, targeting the development and sampling of ultra-high capacity 64 terabyte (TB) SSDs in the second quarter.

In mid-May, Samsung even revealed the target to release advanced NAND Flash with over 1000 layers by 2030. According to an earlier report by Wccftech, the South Korean memory giant plans to apply new ferroelectric materials on the manufacturing of NAND.

On the other hand, the current HBM3 supply for NVIDIA’s H100 solution is primarily met by SK Hynix, leading to a supply shortfall in meeting burgeoning AI market demands. After establishing its leadership in HBM, it is reported that SK Hynix now aims to dominate the AI memory market in NAND as well, according to Business Korea.

It is worth noting that SK Hynix recently achieved a breakthrough with the development of “Zoned UFS 4.0” (ZUFS 4.0), an on-device AI mobile NAND solution tailored for AI-capable smartphones, which is scheduled to start mass production in the third quarter, according to TheElec.

(Photo credit: Samsung)

According to a report from global media Reuters, the Indian software company Zoho plans to invest USD 700 million in the chip manufacturing sector.

Founded in 1996 and currently headquartered in Tamil Nadu, India, Zoho provides software and related services to businesses across 150 countries.

Zoho is considering the production of compound semiconductors and is seeking incentives from the Indian government. The proposal is currently being reviewed by the committee responsible for promoting India’s chip initiative under the Ministry of Electronics and Information Technology.

Compound semiconductors are semiconductor materials composed of two or more different elements. Compared to traditional silicon (Si) semiconductors, compound semiconductors generally boast higher electron mobility, wider bandgap, and better thermal stability and radiation resistance. These properties make them suitable for applications that require high speed, high frequency, high temperature, and high efficiency. Compound semiconductor materials abound, among which silicon carbide (SiC) and gallium nitride (GaN) are representatives. Currently, both materials are sought-after in consumer electronics and EV markets.

In recent years, India has actively promoted chip assembly and local production as a way of becoming a key player in global semiconductor market. The industry source points out that India’s chip initiative aims to strengthen the country’s position and competitiveness in global semiconductor industry through increased investment, international cooperation, infrastructure development, and talent cultivation.

In February 2024, India approved a semiconductor manufacturing investment plan totaling INR 1.26 trillion (USD 15.2 billion), covering wafer fabrication and chip packaging sectors, inclusive of India’s first fab, a collaboration between Tata Group and Powerchip.

The plant is expected to produce 50,000 wafers per month, covering multiple mature nodes including 28nm, 40nm, 55nm, 90nm, and 110nm. The goal is to produce 3 billion chips annually for various segments, such as high-power computing, EV, telecommunication, and power electronic.

Read more

• [News] 12-Inch Wafer Capacity Construction Going Full Steam
• [News] PSMC Collaborates with Tata to Establish India’s First Fab

(Photo credit: iStock)

Intel’s early adoption of ASML’s High Numerical Aperture Extreme Ultraviolet Lithography (High-NA EUV) equipment is seen by many as a crucial move for Intel to reclaim its technological leadership. Yet, according to a report from CNA, industry sources cited in the report have warned that the high cost of High-NA EUV could lead Intel to face the dilemma of expanding losses.

As Intel secures High-NA EUV equipment, the Korean media outlet TheElec reported that ASML plans to manufacture five High-NA EUV equipment this year, all of which have been booked by Intel. TSMC’s decision to continue using existing EUV equipment for its A16 process, rather than adopting High-NA EUV, has drawn significant attention and sparked lively discussion.

Per a report from Reuters, Intel CEO Pat Gelsinger has acknowledged that the previous decision to oppose using ASML’s EUV equipment was a mistake, which hampered the profitability of Intel’s foundry business. He stated that, with the adoption of EUV equipment, Intel is now highly competitive in terms of price and performance. There is widespread interest in whether Intel’s early adoption of High-NA EUV equipment will help it regain its position as a technology leader.

On the other hand, TSMC plans to mass-produce its A16 technology by 2026, combining nanosheet transistors with a supertrack architecture, garnering attention from the industry.

Ray Yang, the consulting director at Industry, Science and Technology International Strategy Center of ITRI (Industrial Technology Research Institute), stated that TSMC’s decision not to adopt High-NA EUV equipment for the A16 process was likely made after a comprehensive evaluation.

Yang mentioned that TSMC is undoubtedly aware of the benefits that High-NA EUV equipment can bring. However, given the high costs, TSMC has chosen to meet its customers’ diverse needs through other means.

According to ASML, High-NA EUV equipment increases the numerical aperture from 0.33 to 0.55, providing higher-resolution imaging capabilities. This improvement enhances precision and clarity, simplifies the manufacturing process, reduces production time, and boosts production efficiency.

During a technical symposium in Amsterdam on May 14th, TSMC’s Senior Vice President of Business Development and Co-Chief Operating Officer, Dr. Kevin Zhang, remarked that ‘I like the high-NA EUV’s capability, but I don’t like the sticker price.’

Each EUV system from ASML costs around USD 180 million, while High-NA EUV equipment is priced at USD 380 million, more than double the cost of EUV.

Ray Yang noted that the importance of advanced semiconductor packaging is increasing and will play a crucial supporting role. He argued that Intel’s rush to acquire High-NA EUV equipment is a case of choosing the wrong battlefield and weapon because High-NA EUV equipment is not the sole decisive factor for future success.

Ray Yang stated that as the global leader in semiconductor foundry services, TSMC has numerous customers, a comprehensive ecosystem, and ample capital. If customers demand and are willing to pay higher prices, TSMC will undoubtedly adopt High-NA EUV equipment.

Yang noted that TSMC is taking a cautious approach to adopting High-NA EUV equipment, likely after thoroughly considering its necessity. If Intel makes significant purchases of High-NA EUV equipment, its future capacity utilization will be worth observing, as it might face the risk of increased losses.

Currently, both TSMC and Samsung utilize EUV equipment for manufacturing, covering TSMC’s 7nm, 5nm, and 3nm processes and Samsung’s EUV Line (7nm, 5nm, and 4nm) located in Hwaseong, Korea, along with the 3nm GAA process.

Read more

• [News] How Costly is the High-NA EUV? TSMC Reportedly Shocked, Considering Not Using the Equipment in its A16 Node
• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix

(Photo credit: ASML)